What’s being touted as “the industry’s first dual 100 Gbps Gearbox solution for connecting 100G interfaces with the newest generation of high-density, 100 Gbps CFP2 optical modules” was unveiled by Xilinx Inc. earlier today.

Incorporating a single 28nm Virtex-7 HT FPGA and Xilinx Gearbox intellectual property (IP) cores, “the solution overcomes the initial hurdles of leveraging the new CFP2 optics supporting 100GE, OTU4 and 10x 10 MSA specifications,” the company says. “This allows higher-density 100G line cards and transmission equipment while lowering overall system power consumption and solution cost through integration.”

The Dual 100G Gearbox solution includes the Gearbox IP cores for dual 100 Gbps channels supporting two CFP2 and future CFP4 optical modules and the Virtex-7 HT FPGA silicon (7VH290T, 7VH580T or 7VH870T). The solution maps data between the 10 and four serial lane interfaces in both ingress and egress directions, and it converts data streams of either CAUI (10x 10.3125G) or OTL4.10 (10x 11.18G) to four lanes of proposed CAUI4 (4x 25.78G) or OTL4.4 (4x 27.95G).

“In the case of 100GE, the original 20 PCS lanes are reconstructed internally, allowing per-lane debug, skew insertion, and data manipulation, all under user control,” Xilinx adds.

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